1. Field of the Invention
The present invention relates to a microcrystalline silicon thin film transistor and a method for manufacturing the same. More particularly, the present invention relates to a top gate microcrystalline silicon thin film transistor and a method for manufacturing the same.
2. Description of the Related Art
The low temperature polysilicon thin film transistors (LTPS-TFTs) compared to the conventional amorphous silicon thin film transistor has higher electron mobility and better reliability. At present, the polysilicon thin film manufacturing process is performed mostly by solid phase crystallization or costly excimer laser annealing method. The solid phase crystallization needs higher crystallization temperature and thus requires a silicon wafer or a quarts wafer as a substrate. The cost is expensive and inappropriate to large-area production. The excimer laser annealing method can lower the crystallization temperature, but requiring expensive equipments. The throughput is also not high. As to the microcrystalline silicon thin film transistor manufactured by the plasma enhanced chemical vapor deposition system conventionally continues the structure of the bottom gate type device. Please refer to FIG. 1, generally during the growth of the microcrystalline silicon layer (μc-Si layer) 103, an amorphous incubation layer 102 is formed between an insulating layer 101 and the microcrystalline silicon thin film 103, resulting in an inversion channel region of a microcrystalline silicon thin film transistor subsequently completed is formed in the amorphous incubation layer 102 and can not be formed in a crystallized thin film. The microcrystalline silicon thin film transistor device would not have good electrical performance.
FIG. 2 is a schematic cross-sectional view of a conventional bottom gate microcrystalline silicon thin film transistor, including a substrate 200, a pair of microcrystalline silicon layer containing n+ dopants 204a and 204b, and a pair of source/drain metal electrodes 205a and 205b. The bottom gate electrode 201 is positioned on the substrate 200, and the insulating layer 202 is positioned on the bottom gate electrode 201. The microcrystalline silicon layer 203 is positioned on the insulating layer 202, and the microcrystalline silicon layers containing n+ dopants 204a and 204b are respectively positioned on the microcrystalline silicon layer 203 at two opposite sides of the bottom gate electrode 201. The pair of the source/drain metal electrodes 205a and 205b is respectively positioned on one of the pair of the microcrystalline silicon layers containing n+ dopants 204a and 204b. The pair of the source/drain metal electrodes 205a and 205b respectively forms ohmic contact with an overlying electrical contact (not shown). An inversion channel region of the bottom gate microcrystalline silicon thin film transistor is formed in an interface between the insulating layer 202 and the bottom portion of the microcrystalline silicon layer 203. The conventional bottom gate microcrystalline silicon thin film transistor can directly employ the plasma enhanced chemical vapor deposition method to sequentially grow the insulating layer 202, the microcrystalline silicon layer 203 and the pair of the microcrystalline silicon layer containing n+ dopants 204a and 204b. During the sequential growth of various thin films, an amorphous incubation layer is formed in an interface between the insulating layer 202 and the microcrystalline silicon layer 203, as shown in FIG. 1, and resulting in the inversion channel region of the bottom gate microcrystalline silicon thin film transistor can not be formed in a crystallized layer. The electrical performance of the bottom gate microcrystalline silicon thin film transistor would not be good.